1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, in particularly, to an STI structure having a preferable surface shape and a method of manufacturing the same.
2. Description of the Related Art
An element isolation technique is known as one of the important techniques to achieve a high integration density of an LSI. In the isolation technique, a shallow trench isolation (STI) structure is mainly used. However, although, at the present, a ratio of a trench width to a trench depth (aspect ratio) increases, STI filling cannot be easily performed without forming a void or a seam in a TEOS/O3 film obtained by a conventional normal-pressure CVD method, an HDP-TEOS film obtained by a plasma CVD method, or the like. Especially, in the STI filling of an NAND flash memory, a silicon oxide film must be filled in the form of a high aspect and taperless STI shape as compared to a logic device. For this reason, it is difficult from 90-70-nm-width generation that a high density plasma (HDP) single-layer oxide film, which does not pose any problem in 130-nm-width generation, is once filled in the STI structure.
As a countermeasure against the above problem, an STI filling technique using a coating film has been developed. For example, after an HDP film is formed in a trench having a depth of 350 to 450 nm from a floating gate surface to an STI bottom, a coating film of a perhydro-silazane polymer (Polysilazane to be referred as PSZ hereinafter) solution is formed and etched back by devising wet etching, so that a level of STI filling may be controlled.
However, in a trench having a narrow STI width, a wet etching rate of the PSZ film is considerably higher than that of the HDP film. In particular, when an etching solution containing hydrogen fluoride is used for the STI structure having a width of about 90 nm, a large etching rate difference of 2.5 times or more is generated. Therefore, the PSZ film is mainly etched, and the HDP film filled in the STI trench of the semiconductor substrate is thinly left on a side surface of a floating gate (FG) formed through a tunnel insulating film, or the HDP film is partially left in the shape of a taper on the side surface of the floating gate.
Depression of the STI filling material surface is caused by the etching rate difference because the PSZ film is not sufficiently transformed into SiO2. In order to decrease the etching rate of the PSZ film in the step of densifying the SiO2 film, a method of planarizing and then densifying the SiO2 film is proposed. However, even in this method, when the STI trench width is about 100 nm or less, oxygen (O2) required to sufficiently transform the PSZ film into the SiO2 film is not deeply supplied to the STI trench, and the situation of wet etching controllability is still difficult.
In order to secure the drivability of the control gate on the floating gate side surface, an improved shape (tapered shape having a thin HDP film) is very difficult to be formed in a wafer plane or between wafer planes with good controllability. For this reason, even though a control gate (CG) is formed on the floating gate and the filled HDP film through an ONO film and an interlayer insulating film is formed on the control gate, a ratio (coupling ratio) of a coupling capacitance C2 between the floating gate (FG) and the control gate (CG) and a coupling capacitance C1 between the floating gate (FG) and the substrate may fluctuate to cause a decrease in yield.
Furthermore, when a fine device structure advances, the STI filled surface depressed in a concave shape is close to the level of a tunnel oxide film to cause deterioration of a breakdown voltage between the substrate and the control gate. In this manner, at the present, an STI technique of 90-70-nm-width generation or later is not established, and a technique which can easily control an STI filling level and the planarity is demanded.
As a technique that fills the trench with the HDP film, the following technique is disclosed in Jap. Pat. Appln. KOKAI Publication No. 2002-208629. That is, the HDP oxide film is coated on the substrate surface until a trench opening is sealed, and an oxide film near the opening is removed. Thereafter, an HDP oxide film is coated again to fill the trench with the HDP oxide film.